Semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. Integrated circuits (IC) design and fabrication technologies have been exploited to a limit and need more tuning in designing and also interactions between designing and manufacturing.
Accurate simulation of today's devices needs to account for real device geometry complexities after the lithography and etching processes, especially when the channel length shrinks to 65-nm and below. The device performance is believed to be quite different from what designers expect in the conventional IC design flow. The traditional design lacks consideration of the photolithography effects and pattern geometrical operations from the manufacturing side.
For the deep sub-micron circuit design, a purely rectangular shape is almost impossible to achieve in manufacturing. A potential risk is hence imposed on the linkage between design and manufacturing. However, there is no additional parameter in the current SPICE model card to describe the effect of shape distortions. For example, the corner rounding of the L-shape Active region near the poly-silicon gate will be different from that of the T-shaped Active region. The same issue arises in poly-silicon with a hammerhead near the gate area. Several works have attempted to model or characterize non-rectangular devices by slicing a transistor into small parallel devices, and then summing up the currents contributed from those small sliced transistors. This old approach is intuitive but lacks proper models to accurately describe the narrow width and short channel effects of sliced devices. In addition, the sliced devices might fall into the sub-ground region with dimensions less than the minimum of the binning boundary of the SPICE model.
In current digital IC design flow, there are several commercial tools utilized to do the physical checking of devices, such as the well-known DRC rules or further advanced DFM lithography hotspot check rules. Designers have to modify the layout once the layout violates the physical design rules. However, all the methods mentioned are rule-based approaches. There are no tools that can provide a real time electrical performance check for designers. Another disadvantage of the current approaches is that they cannot deal with complicated circuit layout environments. Moreover, there is a limitation on the grid resolution of the database libraries for current rule-based approaches.